1. Field of the Invention
The present invention relates to a digital filter, and more particularly, to an interpolating filter system.
2. Background of the Related Art
FIGS. 1A and 1B are block diagrams of related art data interpolating filters. A zero padding block 1 up-samples twice the received data for padding zero between the data. First and second adapters 3 and 4 filter the data over-sampled in the zero padding block 1. A first delaying block 2 delays the data over-sampled in the zero padding block 1 by one sample unit and provides the delayed data to the first adapter 3. Second and third delaying blocks 5 and 6 delay the data fed back from the first and second adapters 3 and 4 by two sample units, and provide the delayed fed back data to the first and second adapters 3 and 4, respectively. An adder 7 adds the data filtered by the first and second adapters 3 and 4. Each of the first and second adapters 3 and 4 is provided with two input terminals and two output terminals, has a filter coefficient that provides a proper filter characteristic, and includes an adder and a multiplier.
In the aforementioned data interpolating filter, the received data is up-sampled in the zero padding block 1 and provided to the first adapter 3 and the second adapter 4. The data provided to the first adapter 3 is delayed by one sample unit by the delaying block 2. The delayed data provided to the first adapter 3 and the data provided to the second adapter 4 are filtered by the first and second adapters. The filtered data from the first and second adapters 3 and 4 are added by adder 7. In addition, filtered data from each of the first and second adapters 3 and 4 is provided to the second and third delayed parts 5 and 6, respectively.
The related art data interpolating filter shown in FIG. 1B is a modified version of the related art data interpolating filter shown in FIG. 1A. Each of the first and second adapters 8 and 9 has a proper filter coefficient for filtering received data, and first and second delaying blocks 10 and 11 delay the data from the first and second adapters 8 and 9 by one sample unit, and feed back the delayed data to the first and second adapters 8 and 9. A first zero padding block 12 twice up-samples the data filtered in the first adapter 8 and pads zero between the data. A second zero padding block 13 twice up-samples the data filtered in the second adapter 9 and pads zero between the data. A third delaying block 14 delays the data up-sampled in the first zero padding block 12 by one sample unit, and an adder 15 adds the data delayed in the third delaying block 14 and the data from the second padding block 13.
The related art data interpolating filter shown in FIG. 1A positions the first and second zero padding blocks 12 and 13, and the third delaying block 14 downstream of the first and second adapters 8 and 9 for reducing the size of the first and second delaying blocks 10 and 11 that feed back the data from the first and second adapters 8 and 9. Though the data interpolating filters shown in FIGS. 1A and 1B basically have the same function, the data interpolating filter shown in FIG. 1B is preferred because it uses less flipflops.
However, the above-described related art data interpolating filters are complicated in terms of hardware because of the first and second adapters provided on upper and lower sides of the filter. In addition, the above-described related art data interpolating filters are not efficient in terms of data flow because hardware for a mono channel is used even if stereo data is being processed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.